The USB root hub is not a physical device that you plug in a USB peripheral. The USB root hub is the software driver that lets you connect multiple USB peripherals to your computer. Most computers have multiple root hubs so you can share the data bus across multiple devices.
Usually one hub is dedicated to a specific USB version to retain backwards compatibility. For example, USB 2.0 ports are usually supervised by dual controllers. One controller facilitates the faster USB 2.0 data rates while the other one is dedicated to the older, snailish, USB 1.1 standard.
Also, don’t be alarmed if you have more USB root hubs than physical USB ports because a few are probably virtual ports that Window’s needs to be happy.
Today I want to show you how to permanently disable Allow the computer to turn off this device to save power in the Power Management properties of your USB Root Hub.
To see what I’m talking about, click Start and type:
or press the Windows Key + the Pause/Break key on your keyboard.
If you scroll down to Universal Serial Bus controllers and double click one of your USB Root Hubs you’ll see your intractable power option under the Power Management tab.
The problem is that this setting sometimes fails to stick. In other words, after unchecking the power management option, clicking OK, rebooting and revisiting the Device Manager the silly power management option is checked again! It’s like it adamantly refuses to accede to your command!
It fits most of today’s spas up to 96″, all the while offering ease of use and affordability. The Cover Rockit slides effortlessly behind the spa enabling a view from all sides.While the spa is in use the Cover Rockit reduces cover wear and tear by keeping the cover off of the ground. The cover rock-it spa cover lifter canada.
Vexing I know – here’s how to stop the nonsense.
We just need to open your power plan and configure your advanced power settings.
Click the Start button and type
Click Change advanced power settings then scroll down to USB settings and click the little plus next to USB selective suspend setting.
Set both the On battery and Plugged in settings to Disabled then click OK to apply changes.
That should do the trick for ya.
Posted in How To, Windows 7 Tagged with: Tips and Tricks
This article provides information about the communications aspects of Universal Serial Bus, USB: Signaling, Protocols, Transactions.
Signaling (USB PHY)[edit]Signaling rate (transmission rate)[edit]
The theoretical maximum data rate in USB 2.0 is 480 Mbit/s (60 MB/s) per controller and is shared amongst all attached devices. Some personal computer chipset manufacturers overcome this bottleneck by providing multiple USB 2.0 controllers within the southbridge.
According to routine testing performed by CNet, write operations to typical Hi-Speed hard drives can sustain rates of 25–30 MB/s, while read operations are at 30–42 MB/s;[2] this is 70% of the total available bus bandwidth. For USB 3.0, typical write speed is 70–90 MB/s, while read speed is 90–110 MB/s.[2] Mask tests, also known as eye diagram tests, are used to determine the quality of a signal in the time domain. They are defined in the referenced document as part of the electrical test description for the high-speed (HS) mode at 480 Mbit/s.[3]
According to a USB-IF chairman, 'at least 10 to 15 percent of the stated peak 60 MB/s (480 Mbit/s) of Hi-Speed USB goes to overhead—the communication protocol between the card and the peripheral. Overhead is a component of all connectivity standards'.[1] Tables illustrating the transfer limits are shown in Chapter 5 of the USB spec.
For isochronous devices like audio streams, the bandwidth is constant, and reserved exclusively for a given device. The bus bandwidth therefore only has an effect on the number of channels that can be sent at a time, not the 'speed' or latency of the transmission.
Transaction latency[edit]
For low-speed (1.5 Mbit/s) and full-speed (12 Mbit/s) devices the shortest time for a transaction in one direction is 1 ms.[6] High-speed (480 Mbit/s) uses transactions within each micro frame (125 µs)[7] where using 1-byte interrupt packet results in a minimal response time of 940 ns. 4-byte interrupt packet results in 984 ns.[citation needed]
Electrical specification[edit]
USB signals are transmitted using differential signaling on a twisted-pair data cable with 90 Ω ± 15%characteristic impedance.[8]
A USB connection is always between a host or hub at the A connector end, and a device or hub's 'upstream' port at the other end.
Signaling state[edit]
The host includes 15 kΩ pull-down resistors on each data line. When no device is connected, this pulls both data lines low into the so-called single-ended zero state (SE0 in the USB documentation), and indicates a reset or disconnected connection.
Line transition state[edit]
The following terminology is used to assist in the technical discussion regarding USB PHY signaling.
Line state (covering USB 1.x and 2.x)[edit]Gl854g Usb Hub Pid Drive
Transmission[edit]
USB data is transmitted by toggling the data lines between the J state and the opposite K state. USB encodes data using the NRZIline coding:
To ensure that there are enough signal transitions for clock recovery to occur in the bitstream, a bit stuffing technique is applied to the data stream: an extra 0 bit is inserted into the data stream after any occurrence of six consecutive 1 bits. (Thus ensuring that there is a 0 bit to cause a transmission state transition.) Seven consecutively received 1 bits are always an error. For USB 3.0, additional data transmission encoding is used to handle the higher data rates required.
Transmission example on a USB 1.1 full-speed device[edit]
Example of a Negative Acknowledge packet transmitted by USB 1.1 full-speed device when there is no more data to read. It consists of the following fields: clock synchronization byte, type of packet, and end of packet. Data packets would have more information between the type of packet and end of packet.
USB 2.0 speed negotiation[edit]
USB 2.0 devices use a special protocol during reset, called chirping, to negotiate the high bandwidth mode with the host/hub. A device that is USB 2.0 High Speed capable first connects as a Full Speed device (D+ pulled high), but upon receiving a USB RESET (both D+ and D− driven LOW by host for 10 to 20 ms) it pulls the D− line high, known as chirp K. This indicates to the host that the device is high bandwidth. If the host/hub is also HS capable, it chirps (returns alternating J and K states on D− and D+ lines) letting the device know that the hub operates at high bandwidth. The device has to receive at least three sets of KJ chirps before it changes to high bandwidth terminations and begins high bandwidth signaling. Because USB 3.0 uses wiring separate and additional to that used by USB 2.0 and USB 1.x, such bandwidth negotiation is not required.
Clock tolerance is 480.00±0.24 Mbit/s, 12.00±0.03 Mbit/s, and 1.50±0.18 Mbit/s.
Though high bandwidth devices are commonly referred to as 'USB 2.0' and advertised as 'up to 480 Mbit/s,' not all USB 2.0 devices are high bandwidth. The USB-IF certifies devices and provides licenses to use special marketing logos for either 'basic bandwidth' (low and full) or high bandwidth after passing a compliance test and paying a licensing fee. All devices are tested according to the latest specification, so recently compliant low bandwidth devices are also 2.0 devices.
USB 3.0[edit]
USB 3 uses tinned copper stranded AWG-28 cables with 90±7 Ω impedance for its high-speed differential pairs and linear feedback shift register and 8b/10b encoding sent with a voltage of 1 V nominal with a 100 mV receiver threshold; the receiver uses equalization.[9]SSC clock and 300 ppm precision is used. Packet headers are protected with CRC-16, while data payload is protected with CRC-32.[10] Power up to 3.6 W may be used. One unit load in Super Speed mode is equal to 150 mA.[10]
Protocol layer[edit]
During USB communication, data is transmitted as packets. Initially, all packets are sent from the host via the root hub, and possibly more hubs, to devices. Some of those packets direct a device to send some packets in reply.
After the sync field, all packets are made of 8-bit bytes, transmitted least-significant bit first. The first byte is a packet identifier (PID) byte. The PID is actually 4 bits; the byte consists of the 4-bit PID followed by its bitwise complement. This redundancy helps detect errors. (Note also that a PID byte contains at most four consecutive 1 bits, and thus never needs bit-stuffing, even when combined with the final 1 bit in the sync byte. However, trailing 1 bits in the PID may require bit-stuffing within the first few bits of the payload.)
Packets come in three basic types, each with a different format and CRC (cyclic redundancy check):
Handshake packets[edit]
Handshake packets consist of only a single PID byte, and are generally sent in response to data packets. Error detection is provided by transmitting four bits, which represent the packet type twice, in a single PID byte using complemented form. The three basic types are ACK, indicating that data was successfully received; NAK, indicating that the data cannot be received and should be retried; and STALL, indicating that the device has an error condition and cannot transfer data until some corrective action (such as device initialization) occurs.[11][12]
USB 2.0 added two additional handshake packets: NYET and ERR. NYET indicates that a split transaction is not yet complete, while ERR handshake indicates that a split transaction failed. A second use for a NYET packet is to tell the host that the device has accepted a data packet, but cannot accept any more due to full buffers. This allows a host to switch to sending small PING tokens to inquire about the device's readiness, rather than sending an entire unwanted DATA packet just to elicit a NAK.[11][12]
The only handshake packet the USB host may generate is ACK. If it is not ready to receive data, it should not instruct a device to send.
Token packets[edit]
Token packets consist of a PID byte followed by two payload bytes: 11 bits of address and a five-bit CRC. Tokens are only sent by the host, never a device. Below are tokens present from USB 1.0:
OUT, IN, SETUP, and PING token packets[edit]
SOF: Start-of-frame[edit]
SSPLIT and CSPLIT: Start-split transaction and complete split transaction[edit]
Usb Hub With PowerData packets[edit]
A data packet consists of the PID followed by 0–1,024 bytes of data payload (up to 1,024 bytes for high-speed devices, up to 64 bytes for full-speed devices, and at most eight bytes for low-speed devices),[14] and a 16-bit CRC.
There are two basic forms of data packet, DATA0 and DATA1. A data packet must always be preceded by an address token, and is usually followed by a handshake token from the receiver back to the transmitter. The two packet types provide the 1-bit sequence number required by stop-and-wait ARQ. If a USB host does not receive a response (such as an ACK) for data it has transmitted, it does not know if the data was received or not; the data might have been lost in transit or it might have been received but the handshake response was lost.
To solve this problem, the device keeps track of the type of DATAx packet it last accepted. If it receives another DATAx packet of the same type, it is acknowledged but ignored as a duplicate. Only a DATAx packet of the opposite type is actually received.
If the data is corrupted while transmitted or received, the CRC check fails. When this happens, the receiver does not generate an ACK, which makes the sender resend the packet.[15]
When a device is reset with a SETUP packet, it expects an 8-byte DATA0 packet next.
USB 2.0 added DATA2 and MDATA packet types as well. They are used only by high-bandwidth devices doing high-bandwidth isochronous transfers that must transfer more than 1024 bytes per 125 µs micro frame (8,192 kb/s).
PRE packet (tells hubs to temporarily switch to low speed mode)[edit]
A hub is able to support low bandwidth devices mixed with other speed device via a special PID value, PRE. This is required as a USB hub functions as a very simple repeater, broadcasting the host message to all connected devices regardless if the packet was for it or not. This means in a mixed speed environment, there is a potential danger that a low speed could misinterpret a high or full speed signal from the host.
To eliminate this danger, if a USB hub detects a mix of high speed or full speed and low speed devices, it, by default, disables communication to the low speed device unless it receives a request to switch to low speed mode. On reception of a PRE packet however, it temporarily re-enables the output port to all low speed devices, to allow the host to send a single low speed packet to low speed devices. After the low speed packet is sent, an end of packet (EOP) signal tells the hub to disable all outputs to low speed devices again.
Since all PID bytes include four 0 bits, they leave the bus in the full-bandwidth K state, which is the same as the low-bandwidth J state. It is followed by a brief pause, during which hubs enable their low-bandwidth outputs, already idling in the J state. Then a low-bandwidth packet follows, beginning with a sync sequence and PID byte, and ending with a brief period of SE0. Full-bandwidth devices other than hubs can simply ignore the PRE packet and its low-bandwidth contents, until the final SE0 indicates that a new packet follows.
Transaction[edit]OUT transaction[edit]
IN transaction[edit]
SETUP transaction[edit]
This is used for device enumeration and connection management and informs the device that the host would like to start a control transfer exchange.
Setup packet[edit]
A setup transaction transfers an 8-byte setup packet to the device. The setup packet encodes the direction and length of any following data packets.
Control transfer exchange[edit]
The control transfer exchange consist of three distinct stages:
This allows the host to perform bus management action like enumerating new USB devices via retrieving the new device device descriptors. Retrieval of the device descriptors would especially allow for determining the USB Class, VID, and PID, which are often used for determining the correct USB driver for the device.
Also, after the device descriptor is retrieved, the host performs another control transfer exchange, but instead to set the address of the USB device to a new ADDRx.
References[edit]
Retrieved from 'https://en.wikipedia.org/w/index.php?title=USB_(Communications)&oldid=903542677'
Posted byI like Pi2 years ago
Archived
I've got a Raspberry Pi Zero set up with Octopi and need it to connect to a 3D printer, a WiFi dongle and a webcam. I bought a el-cheapo USB hub, stripped the housing off and soldered it to the testpads on the RPi0. The USB and RPi0 both are powered from the same power leads and connected to a lab power supply set to 5V @ 2A.
This works, except for it doesn't. Two ports on the 4 port hub work as intended, the first and the last one, the middle two simply don't work. I've tested this with lsusb and the devices simply don't show up, but they do once I plug them into the working ports.
Initially I suspected that my €2 / $2 hub simply was faulty.. so I bought a new one (same make and model, same chip - HS8836). Same problem. Except this one I've tested on my mac before removing the housing and all ports work as they should and that's when the hub is still unpowered, too. Once I tested it on the RPi0 and saw the same two ports not working again, I reattached the original cable and plugged it into my computer again, where it still works as it should.
I'm kinda lost on this one, I've tried numerous SD cards and various power sources (power bank, plug RPi0 into powered USB hub for power, 2A micro USB powersupplies, etc). I've also tried a few different Raspbian versions, the full Jessie w/ Pixel, Jessie lite and Octopi as well as fresh and known working images. It baffles me. Especially because it worked a week ago..
6 comments
The GL854G is Genesys Logic’s premium 7-port hub solution which fully complies with Universal Serial Bus Specification Revision 2.0. The GL854G implements a multiple TT architecture that provides dedicated TT to each downstream (DS) port, which guarantees Full-Speed(FS) data passing bandwidth when multiple FS device perform heavy loading operations. The controller inherits Genesys Logic’s cutting edge technology on cost and power efficient serial interface design. The GL854G has proven compatibility, lower power consumption figures and better cost structure above all USB 2.0 hub solutions worldwide.
The GL854G implements multiple hub configuration features onto an internal mask ROM, which traditionally requires an external EEPROM. The microprocessor detects general purpose I/O (GPIO) status during the initial stage to configure hub settings such as (1) declaration of compound device (2) gang/individual mode selection…etc. The external EEPROM can be removed if no vendor specified PID/VID or product string is required for the application.
The GL854G provides a 12MHz clock output that can be used as a reference clock source for multi-chip, hub compound applications. The output clock provides enough driving capacity to support up to 2 devices connected to the downstream port
A lower bom cost can be achieved as the GL854 uses a single external 12 MHz crystal / Oscillator clock input, has an On-chip 5V to 3.3V power regulator, with built-in upstream port 1.5K? pull-up and downstream port 15K? pull-down resistors, and supports a low-cost 24C02 EEPROM.
The GL854 is available in a 64 pin LQFP package (7x7mm). Typical applications include, UMPC/MID, motherboard on-board applications, consumer electronics, monitor built-in hub and embedded systems.
Comments are closed.
|
AuthorWrite something about yourself. No need to be fancy, just an overview. ArchivesCategories |